1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device; and more particularly, to a method for fabricating a capacitor of a semiconductor memory device.
2. Description of the Prior Art
A DRAM (Dynamic Random Access Memory) cell is a semiconductor memory device typically comprising of one transistor and one capacitor, in which one bit of data is stored in a cell by using an electric charge. A capacitor comprises of a lower electrode, a dielectric layer, and an upper electrode. One electrode of the capacitor is connected to the source/drain junction of the transistor. Another electrode of the capacitor is connected to a reference voltage line.
Advances in computer applications have increased the demand for higher capacity memory chips. By decreasing the size of the memory cells, more memory cells can be packed into an integrated circuit.
The capacitance of a capacitor is proportional to the surface area of the electrodes and a dielectric constant of a dielectric layer. As the area of the memory cell has decreased, the capacitance of the capacitor tends to decrease. This lowers the performance of the memory cells.
In order to increase the density of the memory cells, stacked capacitors have been proposed. Stacked capacitors are formed by partially stacking the storage electrode over the transistor and over the bit/word line, thereby effectively reducing the area used for each memory cell.
A plug is used to connect the lower electrode of the capacitor with the source/drain junction of the transistor.
A method for fabricating a capacitor of a semiconductor memory device according to the conventional method is described by referring to FIG. 1A to FIG. 1C.
As shown in FIG. 1A, an insulating layer 15 is formed over a semiconductor substrate 10, an isolation layer 11, such as field oxide layer, and a transistor comprising a gate insulating layer 12, a gate electrode 13 and the source/drain junctions 14. Thereafter, a plug 16 is formed in the interlayer insulating layer. The plug 16 is composed of a polysilicon layer 16A, an ohmic contact layer 16B and a diffusion barrier layer 16C formed in a contact hole, exposing one of the source/drain junctions 14.
As shown in FIG. 1B, a lower electrode 17 is formed on the diffusion barrier layer 16C by depositing and patterning a first conductive layer. The diffusion barrier layer 16C may be exposed during the formation of the lower electrode 17 because of a mask misalignment. The mask misalignment frequently occurs in the manufacturing process of the highly integrated device.
As shown in FIG. 1C, a dielectric layer 18 is formed on the lower electrode 17 and an upper electrode 19 is formed on the dielectric layer 18. The dielectric layer 18 is formed with a material exhibiting a very high dielectric constant, such as Barium Strontium Titanate (BaSrTiO3, hereafter abbreviated BST), to increase the capacitance in a highly integrated device.
According to the stated conventional method, the exposed part of the diffusion barrier layer 16C of the plug 16 is contacted to the dielectric layer 18.
There are several problems caused by the contact between the diffusion layer 16C and the dielectric layer 18. One problem is that the diffusion barrier layer 16C is oxidized during the process for forming the dielectric layer 18, because the dielectric layer 18, (such as the BST layer), is formed under an oxygen gas atmosphere and at a high temperature. The oxidized part of the diffusion barrier layer 16C, exhibiting low dielectric constant, plays the role of the dielectric layer of the capacitor, thereby the capacitance of the capacitor is reduced. The other problem is that the work function difference, between the diffusion barrier 16C and the dielectric layer 18, is low. Thus, the leakage current is increased, because of the low Schottky barrier height.
It is, therefore, an object of the present invention to provide a semiconductor memory device and a fabrication method capable of preventing the contact between a dielectric layer of a capacitor and a diffusion barrier of a plug.
It is, therefore, another object of the present invention to provide a semiconductor memory device and a fabrication method capable of preventing a lowering of the capacitance of the capacitor and an increase of the leakage current between the lower electrode of the capacitor and a diffusion barrier of a plug,
In accordance with an aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate.
An interlayer insulating layer is formed over the semiconductor substrate and a plug is formed in the interlayer insulating layer. The plug comprises a diffusion barrier layer and a conducting layer, and wherein the conducting layer is formed with a material capable of current flowing when the conducting layer is oxidized.
A lower electrode of the capacitor is contacted to the conducting layer. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.
In accordance with another aspect of the present invention, there is provided a method for fabricating a semiconductor memory device, comprising the steps of providing a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate.
Another part of the method is to form an interlayer insulating layer over the semiconductor substrate and etching the interlayer insulating layer to form a contact hole. By forming a diffusion barrier layer and a conducting layer in the contact hole a plug is formed, wherein the conducting layer is formed with a material capable of current flowing when the conducting layer is oxidized. A lower electrode is formed and is contacted to the conducting layer. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.
In accordance with a still further aspect of the present invention, there is a method for fabricating a semiconductor memory device. The method includes the steps of providing a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate. Additionally, an interlayer insulating layer is formed over the semiconductor substrate and the interlayer insulating layer is etched to form a contact hole.
A plug is formed out of a diffusion barrier and a conducting layer in the contact hole, and wherein the conducting layer is formed with a material capable of current flowing when the conducting layer is oxidized. Additionally, a seed layer is formed on the conducting layer and a glue layer is formed on the seed layer. The method further includes a sacrificial layer formed on the glue layer. At this point, the sacrificial layer and the glue layer are etched to form an opening defining a region of a lower electrode.
The lower electrode is formed on the seed layer in the opening, and the sacrificial layer and the seed layer are removed to form a dielectric layer on the lower electrode and an upper electrode is formed on the dielectric layer.